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oki semiconductor fedl2250digest-11 issue date: sep. 20, 2007 ml2251/52/53/54/56-xxx, ml22q54/q58 2-channel mixing oki adpcm algorithm-based speech synthesis lsi 1/37 this document contains minimum specifications. for full sp ecifications, please contact your nearest oki office or representative. general description the ml2250 family is a 2-channel mixing speech synthesi s device with an on-chip voice data (i.e., phrases) storing mask rom and a flash memory. besides playing the built-in voice data, this device can output voice data that is input from outside the device. this ml2250 family allows selecting the playback method from the 8-bit pcm, non-linear 8-bit pcm, 16-bit pcm, 2-bit adpcm2, and 4-bit adpcm2 algorithms. and the sound volume is adjustable as well. the ml2250 family incorporates a 14-bit d/a converter and low-pass filter. it is easy to configure a speech synthesizer by externally connecting a power amplifier and a cpu to the ml2250 family. the ml2250 family line-up includes 2 types of products: with on-chip mask rom, and with on-chip flash memory. ? ml2251/52/53/54/56-xxx this is a cmos single chip speech synthesis device with an on-chip mask rom. produc ts with 5 types of mask roms are available in the ml2250 family depending upon the total playback time length. ? ml22q54/q58 the ml22q54/q58 is a speech synthesis device with a 4-mbit flash memory built in. the voice data can be easily written to the flash memory using a special tool. the on-ch ip flash memory product is suitable for the diversified low volume production or short delivery time applications that the on-chip mask rom product cannot support. the ml22q54/q58 is most suitable for evaluation because the circuit configuration is the same as the on-chip mask rom product. as it is easy to write to build in -flash memory, it is able to combine fixed message and variable message.
fedl2250digest-11 oki semiconductor ml2250 family 2/37 table below summarizes the points of difference betwee n the ml2250 family and currently manufactured products with a rom built in. ml2250 family msm6650 family msm9800 family ml2210 family interface parallel or serial parallel, serial or stand-alone parallel or stand-alone serial playback method 2-bit adpcm2 4-bit adpcm2 8-bit pcm 8-bit non-linear pcm 16-bit pcm 4-bit adpcm 8-bit pcm 8-bit pcm 8-bit non-linear pcm 4-bit adpcm 8-bit pcm 8-bit non-linear pcm max. number of phrases 256 127 63 247 sampling frequency (khz) 4.0/5.3/6.0/ 6.4/8.0/10.7 /12.0/12.8/16.0/21.3/ 24.0/25.6/32. 0/42.7/ 48.0 4.0/5.3/6.4/8.0/ 10.7/12.8/16.0/ 32.0 4.0/5.3/6. 4/8.0/10.7/ 12.8/16.0 4.0/5.3/6. 4/8.0/10.7/ 12.8/16.0 clock frequency 4.096 mhz 256 khz (cr oscillation) 4.096 mhz (xt) 256 khz (cr oscillation) 4.096 mhz (xt) 4.096 mhz d/a converter voltage type: 14 bits voltage type: 12 bits current type: 10 bits current type: 12 bits low-pass filter fir type interpolation filter secondary comb filter primary comb filter secondary comb filter number of channels 2 channels 2 channels 1 channel 1 channel phrase control table both 2 channels without user definable phrase restrictions can edit 8 phrases (1 channel only) can edit 8 phrases none volume adjustment 29 steps (?2 db/?5 db steps) 4 steps (?6 db steps) set at vref. set at vref. repeat function no limit 4 types none none stop each channel independent simultaneous channels 1 and 2 available available seam silence interval in continuous playback 0 (note) 4 sampling cycles 3 sampling cycles 4 sampling cycles others external data input possible ? ? ? note: continuous playback shown in the figure below is possible. 1 phrase 1 phrase 1 phrase 1 phrase ml2250 family conventional silence interval no silence interval
fedl2250digest-11 oki semiconductor ml2250 family 3/37 features maximum playback time length (sec) (in 4-bit adpcm2) type rom capacity f sam = 4.0 khz f sam = 6.4 khz f sam = 8.0 khz f sam = 16 khz f sam = 32 khz ml2251 512 kbit 31.7 19.8 15.8 7.9 3.9 ml2252 1 mbit 64.5 40.3 32.2 16.1 8.0 ml2253 3 mbit 195.5 122.2 97.7 48.8 24.4 ml2254 4 mbit 261.1 163.2 130.5 65.2 32.6 ml22q54 4 mbit 261. 1 163.2 130.5 65.2 32.6 ml2256 6 mbit 392.1 245.1 196.0 98.0 49.0 ml22q58 8 mbit 522. 2 326.4 261.0 130.4 65.2 ? non-linear 8-bit pcm, 8-bit pcm, 16-bit pcm, 2-bit adpc m2, and 4-bit adpcm2 algorithms ? serial input/parallel input selectable ? phrase control table function i.e., user definable phrase control table function ? 2 channels mixing function ? master clock frequency: 4.096 mhz ? sampling frequency: 4.0 khz, 5.3 khz, 6.0khz, 6.4 khz, 8.0 khz, 10.7 khz, 12.0khz, 12.8 khz, 16.0 khz, 21.3 khz, 24.0khz, 25.6 khz, 32.0 khz, 42.7 khz, 48 khz ? maximum number of phrases: 256 phrases ? sound volume adjustment function built in (2 sounds independently adjustable in 29 steps) ? external voice data can be input ? 14-bit d/a converter built in ? built-in low-pass filter: digital filter ? package: 44-pin plastic qfp (qfp44-p-910-0.80-2k) (ml2251-xxxga/ ml2252-xxxga/ ml2253-xxxga/ ml2254-xxxga /ml2256-xxxga / ml22q54ga/ml22q58ga) 33-pin w-csp (p-vflga33-5.03x5.78-0.80-w) (ml2253-xxxhb/ ml2254-xxxhb) (ML2256-XXXHB)
fedl2250digest-11 oki semiconductor ml2250 family 4/37 block diagram ml2251/52/53/54-/56xxx xt x t testo2 osc cpu interface 16bit(ml2252) 18bit(ml2254) multiplexer 2bit adpcm2 /4bit adpcm2 synthesizer digital filter 8bit pcm 16bit pcm s y nthesizer&2ch mix timing controller testo1 dv dd dgnd aout reset 16 test 16bit(ml2252) 18bit(ml2254) address controller commnad controller 512kbit(ml2251) 1mbit(ml2252) 3mbit(ml2253) 4mbit(ml2254) 6mbit(ml2256) rom phrase control table loop volume dao ncr1/nd r ncr2/ d l busy 1 b usy2 / er r serial d7/di d6/sc k d5/do d4 d3 d2 d1 d0 w r c s d w r d optana av dd agnd 14bit dac
fedl2250digest-11 oki semiconductor ml2250 family 5/37 ml22q54 xt x t osc cpu interface 18bit multiplexer 2bit adpcm2 /4bit adpcm2 synthesizer digital filter 14bit dac 8bit pcm 16bit pcm s y nthesizer&2ch mix timing controller dv dd dgnd aout reset 16 test 18bit address controller command controller 4mbit rom phrase control table loop volume dao ncr1/nd r ncr2/ d l busy 1 busy2 / er r serial d7/di d6/sc k d5/do d4 d3 d2 d1 d0 w r c s d w r d rd/ b y optana av dd agnd testo
fedl2250digest-11 oki semiconductor ml2250 family 6/37 ml22q58 xt x t osc cpu interface 19bit multiplexer 2bit adpcm2 /4bit adpcm2 synthesizer digital filter 14bit dac 8bit pcm 16bit pcm s y nthesizer&2ch mix timing controller aout reset 16 test 19bit address controller command controller 8mbit rom phrase control table loop volume dao ncr1/nd r ncr2/ d l busy 1 busy2 / er r serial d7/di d6/sc k d5/do d4 d3 d2 d1 d0 w r c s d w r d rd/ b y optana av dd agnd testo regulator dvdd dgnd regout vbg
fedl2250digest-11 oki semiconductor ml2250 family 7/37 pin configuration (top view) ml2251/52/53/54/56-xxxga 44-pin plastic qfp 44 43 42 41 40 39 38 37 36 35 34 nc: no connection nc dv dd xt x t d0 dgnd d1 d2 d3 d4 nc nc dw b usy 1 ncr2/ dl ncr1/ndr rd testo1 testo2 r ese t test nc 1 2 3 4 5 6 7 8 9 10 11 nc serial dgnd a v dd a out dao a gnd d7/di nc d6/sck d5/do 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 nc b usy 2 / err w r nc dv dd dgnd nc optana c s nc nc
fedl2250digest-11 oki semiconductor ml2250 family 8/37 ml22q54ga 44-pin plastic qfp nc: no connection nc dv dd xt x t d0 dgnd d1 d2 d3 d4 nc nc dw b usy 1 ncr2/ dl ncr1/ndr rd testo rd/ by r ese t test nc 1 2 3 4 5 6 7 8 9 10 11 nc serial dgnd a v dd a out dao a gnd d7/di nc d6/sck d5/do 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 nc b usy2 / err w r nc dv dd dgnd nc optana c s nc nc 44 43 42 41 40 39 38 37 36 35 34
fedl2250digest-11 oki semiconductor ml2250 family 9/37 ml22q58ga 44-pin plastic qfp nc: no connection nc dv dd xt x t d0 dgnd d1 d2 d3 d4 nc nc dw b usy 1 ncr2/ dl ncr1/ndr rd testo rd/ by r ese t test nc 1 2 3 4 5 6 7 8 9 10 11 nc serial dgnd a v dd a out dao a gnd d7/di nc d6/sck d5/do 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 nc b usy2 / err w r vbg dv dd dgnd regout optana c s nc nc 44 43 42 41 40 39 38 37 36 35 34
fedl2250digest-11 oki semiconductor ml2250 family 10/37 ml2253/54-xxxhb 33pin w-csp(bottom view) d5/do d3 d1 dgnd xt xt 6 d6/sck d4 d2 d0 dvdd test 5 agnd d7/di reset testo2 4 dao aout ncr1/ndr testo1 rd 3 avdd dgnd cs wr busy1 ncr2/ dl 2 serial optana dgnd dvdd dw busy2 / err 1 f e d c b a
fedl2250digest-11 oki semiconductor ml2250 family 11/37 ML2256-XXXHB 33pin w-csp (bottom view) d5 d3 gnd xt xt 7 d6 d4 d1 d0 vdd 6 agnd d7 d2 test reset 5 dao testo2 testo1 rd 4 aout dw ncr2/dl ncr1/ndr 3 avdd serial optana wr busy1 2 gnd cs gnd vdd busy2/err 1 e d c b a
fedl2250digest-11 oki semiconductor ml2250 family 12/37 pin descriptions-1 ml2251/52/53/54/56-xxxga and ml2253/54/56-xxxhb common pins qfp pin wcsp pin ml2256 wcsp pin symbol type description 43 a1 a1 busy2 / er r o when using the built-in rom for voice output, this pin outputs ?l? level while channel 2 side processes a command and while plays back voice. works as err pin when using the ext command for voice output. if an abnormality occurred in the transfer of data, the pin will output ?l? level and the voice output may become noisy. ?h? level at power on. 3 b2 a2 busy1 o outputs ?l? level while the channel 1 side processes a command and plays back voice. ?h? level at power on. 4 a2 b3 ncr2/ dl o the command input of channel 2 side is valid at ?h? level when using the built-in rom for voice output. works as dl pin when using ext command for the voice output. this pin outputs the signal that captures voice data to inside. the data is captured inside on the rising edge of dl . ?h? level at power on. 5 c3 a3 ncr1/nd r o the command input of channel 1 side is valid at ?h? level when using the built-in rom for voice output. works as ndr pin when using ext command for the voice output. the voice data input is valid at ?h? level. ?h? level at power on. 9 b4 a5 reset i at ?l? level input, the device enters the initial state; the oscillation stops, and aout output and daq output are gnd level at this time. 10 a5 b5 test i test pin for the device. input ?l? level to this pin. this pin has a pull-down resistor built in. 14 a6 a7 xt i wired to a crystal or ceramic oscillator. a feedback resistor of around 1 m ? is built in between this xt pin and xt pin (pin 15). when using an external clock, input the clock from this pin. 15 b6 b7 xt o wired to a ceramic or crystal oscillator. when using an external clock, keep this pin open. 16 18 19 20 e6 d5 d6 c5 d7 c5 c6 b6 d3 d2 d1 d0 i/o cpu interface data bus pins in the parallel input interface. channel status output pins at rd pin = ?l? level. in the serial input interface, keep these pins at ?l? level. 21 e5 d6 d4 i/o cpu interface data bus pin in the parallel input interface. when rd pin is at ?l? level, this pin d4 usually outputs ?l? level. in the serial input interface, keep this pin at ?l? level. 23 f6 e7 d5/do i/o cpu interface data bus pin in the parallel input interface. when rd pin is at ?l? level, this d5/do pin usually outputs ?l? level. works as channel status output pin in the serial interface. when cs and rd pins are ?l? level, the status of each channel is output serially from this d5/do pin in synchronization with sck clock.
fedl2250digest-11 oki semiconductor ml2250 family 13/37 qfp pin wcsp pin ml2256 wcsp pin symbol type description 24 f5 e6 d6/sck i/o cpu interface data bus pin in the parallel input interface. usually outputs ?l? level when rd = ?l? level. works as serial clock input pin in the serial input interface. when the sck input is at ?l? level on the falling edge of wr, rd, dw , the di input is captured in the device on the rising edge of sck clock. and when the sck input is at ?h? level on the falling edge of wr, rd, dw , the di input is captured on the falling edge of sck clock. 26 c4 d5 d7/di i/o cpu interface data bus pin in the parallel input interface. usually output ?l? level when rd is at ?l? level. works as serial data input pin in the serial input interface. 28 f3 e4 dao o dao pin outputs analog signal of 14-bit dac. 29 e3 e3 aout o aout pin usually outputs the analog signal of 14-bit dac via voltage follower. 32 f1 d2 serial i cpu interface switching pin. serial input interface at ?h? level. and parallel input interface at ?l? level. 36 d2 d1 cs i cpu interface chip select pin. when cs pin is at ?h? level, the wr , dw , and rd signals cannot be input to the device. 37 e1 c2 optana i keep this pin ?l? level. the analog signal of 14-bit dac is output from dao pin and from aout pin via voltage follower. 42 c2 b2 wr i cpu interface write signal. when cs pin is at ?h? level, the wr signal cannot be input to the device. 2 b1 c3 dw i data write signal when using ext command for the voice output. set the pin to ?h? level when not using ext command. when cs pin is at ?h? level, the dw signal cannot be input to the device. this pin has a pull-up resistor built in. 6 a3 a4 rd i cpu interface read signal. when cs pin is at ?h? level, the rd signal cannot be input to the device. this pin has a pull-up resistor built in. 7, 8 b3, a4 b4 c4 testo1 testo2 o output pin for testing. keep this pin open. 30 f2 e2 av dd ? analog power supply pin. insert a 0.1 f or larger bypass capacitor between this pin and agnd pin. 13, 40 b5, c1 a6,b1 dv dd ? digital power supply pin. insert a 0.1 f or larger bypass capacitor between this pin and dgnd pin. 27 f4 e5 agnd ? analog ground pin. 17, 31, 39 c6, d1, e2 c1,c7,e1 dgnd ? digital ground pin.
fedl2250digest-11 oki semiconductor ml2250 family 14/37 pin descriptions-2 ml22q54/q58ga common pins 44-pin plastic qfp pin symbol type description 43 busy2 / err o when using the built-in rom for voice output, this pin outputs ?l? level while channel 2 side processes a command and while plays back voice. works as err pin when using ext command for the voice output. if an abnormality occurred in the transfer of data, the err pin outputs ?l? level and the voice output may become noisy. ?h? level at power on. 3 busy1 o outputs ?l? level while the channel 1 side processes a command and while plays back voice. ?h? level at power on. 4 ncr2/ dl o the input command of channel 2 is valid at ?h? level when using the built-in rom for voice output. dl pin when using ext command for the voice output. it outputs the voice data capture signal. the data is captured on the rising edge of dl . ?h? level at power on. 5 ncr1/ndr o the command input of channel 1 side is valid at ?h? level when using the built-in rom for voice output. ndr pin when using ext command for the voice output. the voice data input is effective at ?h? level. ?h? level at power on. 9 reset i when ?l? level is input to this pin, the device is reset, the oscillation stops, and aout and daq outputs go into gnd level. 10 test i test pin for the device. input ?l? level to this pin. this pin has a pull-down resistor built in. 14 xt i wired to a crystal or ceramic oscillator. a feedback resistor of around 1 m ? is built in between this xt pin and xt pin (pin 15). when using an external clock, input the clock from this pin. 15 xt o wired to a ceramic or crystal oscillator. when using an external clock, keep this pin open. 16 18 19 20 d3 d2 d1 d0 i/o cpu interface data bus pins in the parallel input interface. channel status output pins when rd is at ?l? level. the pins output the flash memory data when reading the built-in flash memory data. in the serial input interface, keep these pins at ?l? level. 21 d4 i/o cpu interface data bus pin in the parallel input interface. the pin outputs flash memory data when reading the built-in flash memory data. when rd is at ?l? level other than when reading the flash memory data, this pin usually outputs ?l? level. in the serial input interface, keep this pin at ?l? level. 23 d5/do i/o cpu interface data bus pin in the parallel input interface. the pin outputs flash memory data when reading the built-in flash memory data. when rd is at ?l? level other than when reading the flash memory data, this pin usually outputs ?l? level. channel status output pin in the serial input interface. when cs and rd are at ?l? level, this d5/do pin serially outputs the status of each channel in synchronization with sck clock. when reading data of the built-in flash memory, the pin will output serially the flash memory data.
fedl2250digest-11 oki semiconductor ml2250 family 15/37 pin symbol type description 24 d6/sck i/o works as cpu interface data bus pin in parallel input interface. works as flash memory data output pin when reading the built-in flash memory data. when rd is at ?l? level other than when reading the flash memory data, this d6/sck pin usually outputs ?l? level. works as serial clock input pin in the serial input interface. when the sck input is at ?l? level on the falling edge of wr, rd, dw , the di input is captured in device on the rising edge of sck clock. and when the sck input is at ?h ? level on the falling edge of cs , the di input is captured on the falling edge of sck clock. 26 d7/di i/o works as cpu interface data bus pin in the parallel input interface. works as flash data output pin when reading the built-in flash memory data. when rd is at ?l? level at times other than reading the flash memory data, this d7/di pin usually outputs ?l? level. works as serial data input pin in the serial input interface. 28 dao o dao pin outputs the 14-bit dac analog signal. 29 aout o aout pin outputs the 14-bit dac analog signal via voltage follower. 32 serial i cpu interface switching pin. at ?h? level: serial input interface. at ?l? level: para llel input interface. 36 cs i cpu interface chip select pin. when cs pin is at ?h? level, the wr , dw , and rd signals cannot be input to the device. 37 optana i keep this pin ?l? level. 14-bit dac analog signal is output from dao pin and 14-bit dac analog signal is out put from aout pin via the voltage follower. 42 wr i cpu interface write signal. when cs pin is at ?h? level, the wr signal cannot be input to the device. 2 dw i speech data write signal when speech is output using the ext command. when the ext command is not used, set this pin at ?h? level. when cs pin is at ?h? level, the dw signal cannot be input to the device. this pin has a pull-up resistor built in. 6 rd i cpu interface read signal. this pin is used when reading the status signal of each channel or when reading data of the built-in flash memory. when not in use, keep this pin to ?h? level. this pin has a pull-up resistor built in. 7 testo o output pin for testing. keep this pin open. 8 rd/by o output pin to indicate the automatic erase/write status of the built-in flash memory. outputs ?l? level during erase or programming cycle to indicate the busy state. goes to ?h? level at the end of the erase or programming cycle and enters into the ready state.
fedl2250digest-11 oki semiconductor ml2250 family 16/37 pin symbol type description 30 av dd ? analog power supply pin. insert a 0.1 f or larger bypass capacitor between this pin and agnd pin. 13, 40 dv dd ? digital power supply pin. insert a 0.1 f or larger bypass capacitor between this pin and dgnd pin. 27 agnd ? analog ground pin. 17, 31, 39 dgnd ? digital ground pin. applicable to ml22q58 pins pin symbol type description 38 regout o 3v regulator output pin for the built-in flash power supplies. connect a 10 f or larger condenser between regout pin and dgnd pin. 41 vbg o reference voltage output pin for regulator. recommends connecting a 150pf condenser between regout pin and dgnd pin.
fedl2250digest-11 oki semiconductor ml2250 family 17/37 absolute maximum ratings (gnd = 0 v) parameter symbol condition rating unit ta = 25c ml2251/52/53/54/56-xxx ml22q58 ?0.3 to +7.0 v power supply voltage v dd ta = 25c, ml22q54 ?0.3 to +4.6 v input voltage v in ta = 25c ?0.3 to v dd +0.3 v ta=25c without ml2253/54-xxxhb 900 ta=25c ml2253/54-xxxhb 660 power dissipation p d ta=25c ML2256-XXXHB 1060 mw ta = 25 c, applies to output pins excluding regout pin 6 ma output short current i sc ta = 25 c, applies to regout pin 45 ma storage temperature t stg ? ?55 to +150 c recommended operating conditions (3 v) ml225152/53/54/56-xxx, ml22q54/q58 (gnd = 0 v) parameter symbol condition range unit ml2251/52/53/54/56-xxx, ml22q54 2.7 to 3.6 v power supply voltage v dd ml22q58 2.7 to 3.3 v ml2251/52/53/54/56-xxx ?40 to +85 operating temperature t op ml22q54/q58 0 to +70 c min. typ. max. master clock frequency f osc ? 3.5 4.096 4.5 mhz recommended operating conditions (5 v) ml2251/52/53/54/56-xxx, ml22q58 (gnd = 0 v) parameter symbol condition range unit power supply voltage v dd ? 4.5 to 5.5 v ml2251/52/53/54/56-xxx ?40 to +85 c ml22q58 0 to +70 c operating temperature t op ml22q58 (writing flash) 0 to +50 c min. typ. max. master clock frequency f osc ? 3.5 4.096 4.5 mhz
fedl2250digest-11 oki semiconductor ml2250 family 18/37 electrical characteristics dc characteristics (3 v) ml2251/52/53/54/56-xxx, ml22q54/q58 ml2251/52/53/54/56-xxx: dv dd = av dd = 2.7 to 3.6 v, dgnd = agnd = 0 v, ta = ?40 to +85c ml22q54: dv dd = av dd = 2.7 to 3.6 v, dgnd = agnd = 0 v, ta = 0 to +70c ml22q58 : dv dd = av dd = 2.7 to 3.3 v, dgnd = agnd = 0 v, ta = 0 to +70c parameter symbol condition min. typ. max. unit ?h? input voltage v ih ? 0.86 v dd ? ? v ?l? input voltage v il ? ? ? 0.14 v dd v ?h? output voltage v oh i oh = ?1 ma v dd ?0.4 ? ? v ?l? output voltage v ol i ol = 2 ma ? ? 0.4 v ?h? input current 1 i ih1 v ih = v dd ? ? 10 a ?h? input current 2 (note 1) i ih2 v ih = v dd 0.3 2.0 15 a ?h? input current 3 (note 2) i ih3 v ih = v dd pull-down resistor built in pin 8 40 130 a ?l? input current 1 i il1 v il = gnd ?10 ? ? a ?l? input current 2 (note 3) i il2 v il = gnd pull-up resistor built in pin ?120 ?40 ?10 a ?l? input current 3 (note 1) i il3 v il = gnd ?15 ?2.0 ?0.3 a i dd1 f osc = 4.096 mhz at no load (ml2251/52/53/54/56-xxx) ? 6 35 ma playback operating current consumption i dd2 f osc = 4.096 mhz at no load (ml22q54/q58) ? 9 35 ma built-in flash memory access operating current consumption 1 i dd3 f osc = 4.096 mhz at no load read operation (ml22q54/q58) ? 10 35 ma built-in flash memory access operating current consumption 2 i dd4 f osc = 4.096 mhz at no load write and erase operation (ml22q54/q58) ? 20 60 ma ta = ?40 to +70c ? ? 15 a ta = ?40 to +85c ? ? 50 a standby current consumption i dds ta = 0 to +70c (ml22q54/q58) ? ? 55 a notes: 1. applies to xt pin. 2. applies to test pin. 3. applies to rd and dw pins.
fedl2250digest-11 oki semiconductor ml2250 family 19/37 dc characteristics (5 v) ml2251/52/53/54/56-xxx, ml22q58 ml2251/52/53/54/56-xxx : dv dd = av dd = 4.5 to 5.5 v, dgnd = agnd = 0 v, ta = ?40 to +85c ml22q58 : dv dd = av dd = 2.7 to 3.3 v, dgnd = agnd = 0 v, ta = 0 to +70c parameter symbol condition min. typ. max. unit ?h? input voltage v ih ? 0.8 v dd ? ? v ?l? input voltage v il ? ? ? 0.2 v dd v ?h? output voltage v oh i oh = ?1 ma v dd ?0.4 ? ? v ?l? output voltage v ol i ol = 2 ma ? ? 0.4 v ?h? input current 1 i ih1 v ih = v dd ? ? 10 a ?h? input current 2 (note 1) i ih2 v ih = v dd 0.8 5.0 20 a ?h? input current 3 (note 2) i ih3 v ih = v dd pull-down resistor built in pin 30 ? 350 a ?l? input current 1 i il1 v il = gnd ?10 ? ? a ?l? input current 2 (note 3) i il2 v il = gnd pull-up resistor built in pin ?230 ? ?60 a ?l? input current 3 (note 1) i il3 v il = gnd ?20 ?5.0 ?0.8 a i dd1 f osc = 4.096 mhz at no load (ml2251/52/53/54/56-xxx) ? 19 40 ma operating current consumption i dd2 f osc = 4.096 mhz at no load (ml22q58) ? 22 40 ma built-in flash memory access operating current consumption 1 i dd3 f osc = 4.096 mhz at no load read operation (ml22q58) ? 23 40 ma built-in flash memory access operating current consumption 2 i dd4 f osc = 4.096 mhz at no load write and erase operation (ml22q58) ? 33 60 ma ta = ?40 to +70c ? ? 15 a ta = ?40 to +85c ? ? 100 a standby current consumption i dds ta = 0 to +70c (ml22q58) ? ? 100 a notes: 1. applies to xt pin. 2. applies to test pin. 3. applies to rd and dw pins.
fedl2250digest-11 oki semiconductor ml2250 family 20/37 analog section characteristics (3 v) ml2251/52/53/54/56-xxx, ml22q54/q58 ml2251/52/53/54/56-xxx: dv dd = av dd = 2.7 to 3.6 v, dgnd = agnd = 0 v, ta = ?40 to +85c ml22q54: dv dd = av dd = 2.7 to 3.6 v, dgnd = agnd = 0 v, ta = 0 to +70c ml22q58 : dv dd = av dd = 2.7 to 3.3 v, dgnd = agnd = 0 v, ta = 0 to +70c parameter symbol condition min. typ. max. unit aout output load resistance r lao ? 50 ? ? k ? aout output voltage range v aout no output load 0.5 ? av dd ?0.5 v dao output impedance r dao ? 30 50 70 k ? analog section characteristics (5 v) ml2251/52/53/54/56-xxx, ml22q58 ml2251/52/53/54/56-xxx : dv dd = av dd = 4.5 to 5.5 v, dgnd = agnd = 0 v, ta = ?40 to +85c ml22q58 : dv dd = av dd = 2.7 to 3.3 v, dgnd = agnd = 0 v, ta = 0 to +70c parameter symbol condition min. typ. max. unit aout output load resistance r lao ? 50 ? ? k ? aout output voltage range v aout no output load 0.5 ? av dd ?0.5 v dao output impedance r dao ? 30 50 70 k ? regout output voltage v rego ml22q58 2.7 3 3.3 v vbg output voltage v bg ml22q58 1.0 1.3 1.5 v
fedl2250digest-11 oki semiconductor ml2250 family 21/37 functional description micro-computer interface the micro-computer interface in the ml2250 family has 2 types of inte rface circuits built in: parallel interface and serial interface. the interface setting can be changed with the serial pin. serial pin = "h" level: serial interface serial pin = "l" level: parallel interface table below shows the serial pin status in the serial and parallel interfaces. serial = ?l? serial = ?h? parallel interface serial interface d7 (i/o) d (i) serial data input pin d6 (i/o) sck (i) serial clock input pin d5 (i/o) do (o) serial data output pin d4 (i/o) d4 (i) not used. (input ?l? level.) d3 (i/o) d3 (i) not used. (input ?l? level.) d2 (i/o) d2 (i) not used. (input ?l? level.) d1 (i/o) d1 (i) not used. (input ?l? level.) d0 (i/o) data input/output pins d0 (i) not used. (input ?l? level.) 1. parallel interface when selecting the parallel interface, the i/o pins cs , wr, dw , d7 to d0, and rd are used as input pins to input various commands and data, and as output pins to read out the status of the commands and data input. the micro-computer interface becomes effective when the cs pin is set to ?l? level. when a command or data is input, the input data to d7 through d0 pins is captured inside the device on the rising edge of the wr pin. the dw pin is used to input data after having input the ext or flash i/f command. the method to input data to the dw pin is the same as the method to input command from the wr pin. to read the channels status, pins cs and rd are made ?l? level. by doing so , the status signals (ncr1, ncr2, busy1 , busy2 ) of each channel are output to d3 through d0 pins. d7 to d4 pins usually output ?l? level. command and data input timing cs (i) w r , dw (i) d7 to d0 (i/o) data stable
fedl2250digest-11 oki semiconductor ml2250 family 22/37 status read timing table below shows the contents of each data output when readin g the status of the channels. pin output status signal d7 ?l? level d6 ?l? level d5 ?l? level d4 ?l? level d3 channel 2 busy output ( busy2 ) d2 channel 1 busy output ( busy1 ) d1 channel 2 ncr output (ncr2) d0 channel 1 ncr output (ncr1) the busy signal outputs ?l? level when either a command is being processed or the playback of a pertinent channel is going on. in other states, the busy signal outputs ?h? level. the ncr signal outputs ?l? level when either a command is being processed or a pertinent channel is in standby for playback. in othe r states, the ncr signal outputs ?h? level. to read out a status after inputting flash i/f command for ml22q54/q58, d7-d0 pins output ?l? level during command processing. after the command processing is completed, d7-d0 pins output ?h? level. c s (i) r d (i) d7 to d0 (i/o) data stable
fedl2250digest-11 oki semiconductor ml2250 family 23/37 2. serial interface when selecting the serial interface, the i/o pins cs , wr , dw , di, sck, rd , and do are used as input pins to input various commands and data, and as output pins to read out the status of the commands and data. the micro-computer interface becomes effective when cs pin is set to ?l? level. to input the commands and data, ?l? level is input to cs and wr pins followed by, from msb, to di pin in synchronization with the input clock signal at sck pin. data at di pin is captured inside the device on the rising or falling edge of the clock at sck pin. and the command is executed on the rising edge of the wr pin. the selection of rising/falling edge of sck clock is determined by the input level of the sck pin on the falling edge of the cs pin. if the sck pin on the falling edge of the cs pin is at ?l? level, the di pin data is captured inside the device on the rising edge of sck clock. conversely, if the sck pin on the falling edge of the cs pin is at ?h? level, then the di pin data is captured on the falling edge of sck clock. use the dw pin to input various data after having input the ext or flash i/f command. the data input method is the same as to input data from the wr pin. the selection of rising/falling edge of sck clock is determined by the input level of the sck pin on the falling edge of the wr pin. if the sck pin on the falling edge of the wr pin is at ?l? level, the di pin data is captured inside the device on the rising edge of sck clock. conversely, if the sck pin on the falling edge of the wr pin is at ?h? level, then the di pin data is captured on the falling edge of sck clock. use the dw pin to input various data after having input the ext or flash i/f command. the data input method is the same as to input data from the wr pin. command and data input timings ? sck rising edge operation ? sck falling edge operation di(i) cs (i) w r , d w (i) d7 sck(i) d6 d5 d4 d3 d2 d1 d0 cs (i) w r , d w (i) d7 sck(i) d6 d5 d4 d3 d2 d1 d0 di(i)
fedl2250digest-11 oki semiconductor ml2250 family 24/37 to read the channel status, input ?l? level to cs and rd pins. dq pin will output the channel status in synchronization with sck clock. the selection of rising/falling edge of sck clock, similar to when inputting the commands and data, is determined by the level at sck pin at the falling edge of rd pin. the status signals in the parallel interface are ou tput to d7 to d0 pins sequentially from d7. status read timing ? sck rising edge operation ? sck falling edge operation do(o) cs (i) rd (i) d7 sck(i) d6 d5 d4 d3 d2 d1 d0 hi-z hi-z do(o) cs (i) rd (i) d7 sck(i) d6 d5 d4 d3 d2 d1 d0 hi-z hi-z
fedl2250digest-11 oki semiconductor ml2250 family 25/37 commands list each command is 1-byte (8 bits) input. play, fadr, muon, and vol only are 2 bytes input. command d7 d6 d5 d4 d3 d2 d1 d0 description pup1 0 0 0 0 ? ? ? ? instantly shifts the power down device to the command standby state. pup2 0 0 0 1 ? ? ? ? suppresses pop noise and shifts the power down device to the command standby state. pdwn1 0 0 1 0 ? ? ? ? instantly shifts the device from the command standby state to the power down state. pdwn2 0 0 1 1 ? ? ? ? suppresses pop noise and shifts the device from the command standby state to power down state. 0 1 0 0 ? ? c1 c0 play f7 f6 f5 f4 f3 f2 f1 f0 inputs the phrase after the playback channel is specified, and then starts the playback. start 0 1 0 1 ? ? c1 c0 playback start command with phrase specification. inputs the phrase after the playback channel is specified, and then starts the playback. playback start command without phrase specification. inputs the phrase with the fadr command and starts the playback on multiple channels at the same time. 0 1 1 0 0 0 c1 c0 fadr f7 f6 f5 f4 f3 f2 f1 f0 phrase specification command. with this command, specifies the playback phrase for each channel. stop 0 1 1 1 ? ? c1 c0 specifies the finish channel and ends the voice. 1 0 0 0 ? ? c1 c0 muon m7 m6 m5 m4 m3 m2 m1 m0 inserts silence time after specifying the channel to insert silence, and then inserts silence. sloop 1 0 0 1 ? ? c1 c0 repeats the playback mode setting command. effective only for the channel being used for playback. cloop 1 0 1 0 ? ? c1 c0 repeat playback mode releasing command. inputting the stop command releases repeat playback mode automatically. 1 0 1 1 ? ? c1 c0 vol ? ? ? v4 v3 v2 v1 v0 specifies the channel whose sound volume is to be set, and then sets the volume of that channel. ext 1 1 0 0 ? ? ? ? inputs voice data from the cpu i/f to play it back. flash i/f 1 1 0 1 be se wr rd performs data read/write/erase of the built-in flash memory. this command cannot be used while the playback is going on. (applicable to the ml22q54/q58.) c1, c0: channel specification (c0 = ?1?: channel 1; ch = ?1?: channel 2; c0, c1 = ?1?: channel 1, channel 2) f7 to f0: phrase address m7 to m0: silence time length x0: releases the repeated playback v4 to v0: sound volume rd, wr, se, be: mode (rd = ?1?: read data; wr = ?1?: write data; se = ?1?: erase sector; be = ?1?: erase block)
fedl2250digest-11 oki semiconductor ml2250 family 26/37 power down function in power down state, the power down function in the de vice stops the internal operation and oscillation, sets aout to gnd, and minimizes the static idd. when an external clock is in use, input ?l? level to the xt pin, so that current does not flow into the oscillation circuit. figure below shows the equivalent circuit of xt and xt pins. initial state at the reset input at the reset input, status of each output pins is described in the table below. output pin status output pin status ncr1 ?h? level xt ?l? level ncr2 ?h? level aout ?l? level busy1 ?h? level dao ?l? level busy2 ?h? level vbg ?l? level regout hi-z level channel status channel status is of 2 types: ncrn and busyn . channel channel status ch1 ncr1 busy1 ch2 ncr2 busy2 ncrn = ?h? indicates that it is possible to input th e play, start and muon commands for the phrase to be played back next for channel n. busyn = ?h? indicates a state in which channel n has not performed voice processing. busyn = ?l? indicates a state in which channel n is performing voice processing. meanwhile, after a command is input, the ncr and busy signals of all channels are at ?l? level during the processing of the command. 1 m ? approx. rese t to master clock inside the device xt xt
fedl2250digest-11 oki semiconductor ml2250 family 27/37 voice synthesis algorithm the ml2250 family contains 5 algorithm types to match the characteristic of playback voice: 2-bit adpcm 2 algorithm, 4-bit adpcm 2 algorithm, 8-bit pcm algorithm, 8-bit non-linear pcm algorithm, and 16-bit pcm algorithm. key feature of each al gorithm is described in the table below. voice synthesis algorithm applied waveform feature oki 2-bit adpcm2 normal voice waveform oki?s specific speech synthesis algorithm of low bit rate with improved 2-bit adpcm. oki 4-bit adpcm2 normal voice waveform oki?s specific speech synthesis algorithm of improved waveform follow-up with improved 4-bit adpcm. oki 8-bit nonlinear pcm high-frequency components inclusive sound effect etc. algorithm which plays back mid-range of waveform as 10-bit equivalent voice quality. 8-bit pcm high-frequency components inclusive sound effect etc. normal 8-bit pcm algorithm 16-bit pcm high-frequency components inclusive sound effect etc. normal 16-bit pcm algorithm memory allocation and creating voice data the internal memory is partitioned into 4 data areas: voi ce (i.e., phrase) control area, test area, voice area, and phrase control table area. the voice control area manages the in the voice area data. it controls the start/end addresses of voice data, usage/not usage of the phrase control table function and so on. the voice control area st ores voice control data for 256 phrases. the test area stores the data for production testing. the voice area stores the voice waveform data. the phrase control table area is used when phrase information for continuously playing back voice phrase is set in the rom data in advance. as for the details, please refer to the phrase control table function. there is no phrase control table area if the phrase control table is not used. the data in the internal memory is created in the fo rmat specified using the dedicated development tool. voice control area (16 kbit fixed) te s t a r e a voice area phrase control table area depends on creation of rom data. 0x00000 0x007ff 0x00800 max: 0x1ffff max: 0x1ffff rom addresses (ml2252) 0x00807 0x00808
fedl2250digest-11 oki semiconductor ml2250 family 28/37 built-in rom usage prohibited area (applies to ml2251/52/53/54/56-xxx, ml22q54/q58) the 8 bytes between the voice control ar ea and the voice area in th e rom, which is used for the test area, is the prohibited area for use. model voice data area usage prohibited area ml2251 00808 to ffff 00800 to 00807 ml2252 00808 to 1ffff 00800 to 00807 ml2253 00808 to 5ffff 00800 to 00807 ml2254, 22q54 00808 to 7ffff 00800 to 00807 ml2256 00808 to bffff 00800 to 00807 ml22q58 00808 to fffff 00800 to 00807 note: the addresses are indicated in hexadecimal notation. playback time and memory capacity the playback time depends upon the memory capacity, sampling frequency, and playback method. the equation showing the relationship is given below. playback time [sec] = (bit length is adpcm, adpcm 2 = 4 bits; pcm = 8 bits.) example: let the sampling frequency is 16 khz and 4-bit adpcm algorithm. if one 8 mbits rom is used, then the playback time is obtained as follows: playback time = ? 131 (sec) the above equation gives the playback time when the phrase control table function is not used. 1.024 (memory capacity ? 16) (kbit) sampling frequency (khz) bit length 1.024 (8192 ? 16) (kbit) 16 (khz) 4 (bit)
fedl2250digest-11 oki semiconductor ml2250 family 29/37 mixing function the ml2250 family can perform simultaneous mixing of 2 channels. it is possible to specify play and stop for each channel separately. ? precautions for waveform clamp at the time of channels mixing when mixing of channels is done, the clamp occurrence possibility increases from the mixing calculation point of view. if it is known beforehand that the clamp will occur, then adjust the sound volume by vol command. ? mixing of different sampling frequency it is not possible to perform analog mixing by a different sampling frequency. when performing analog mixing, the sampling frequency group of the first playback channel is selected. therefore, please note that if analog mixing is performed by a sampling frequency group other than the selected sampling frequency group, then the playback will not be of constant speed: some times faster and at other times slower. the available sampling groups for analog mixing by a different sampling frequency are listed below. 4.0 khz, 8.0 khz, 16.0 khz, 32.0 khz (group 1) 5.3 khz, 10.6 khz, 21.3 khz, 42.7 khz (group 2) 6.0khz, 12.0khz, 24.0khz, 48.0khz (group 3) 6.4 khz, 12.8 khz, 25.6 khz (group 4) figures below show a case when a sampling frequency group played back a different sampling frequency group. channel 1 channel 2 fs = 16.0 khz fs = 25.6 khz (invalid. played back as fs = 32.0 khz.) figure 1 in case a different sampling frequency played back during playback of the other channel playback normal playback if not played back by other channel. channel 1 channel 2 fs = 16.0 khz fs = 25.6 khz (valid) end of channel 1 figure 2 in case a different sampling frequency played back after the end of the other channel
fedl2250digest-11 oki semiconductor ml2250 family 30/37 phrase control table function the phrase control table function makes it possible to pl ay back multiple phrases in succession. the following functions are set using the phrase control table function: ? continuous playback: there is no limit to the number of times a continuous play back can be specified. it depends on the memory capacity only. ? silence insertion function: 4 to 1024 ms using the phrase control table function enables to e ffectively use the memory capacity of voice rom. below is an example of the rom configuration in the case of using the phrase control table function. example 1: phrases using the phrase control table function example 2: example of rom data in case example 1 converted to rom phrase 1 phrase 2 phrase 3 phrase 4 a d a c e b e c phrase 5 d d d b a d b e c d silence a b c d e a ddress control area editing area f
fedl2250digest-11 oki semiconductor ml2250 family 31/37 application circuit example (ml2251/52/53/54/56-xxx, ml22q54) parallel interface serial interface aout r ese t c s wr r d d7-0 ncr1 ncr2 b usy 1 b usy 2 serial optana xt xt mcu 8 4.096mhz 30pf 30pf amplifier aout r ese t c s wr r d sck di do ncr1 ncr2 b usy 1 b usy 2 serial optana xt xt mcu 4.096mhz 30pf 30pf amplifier
fedl2250digest-11 oki semiconductor ml2250 family 32/37 application circuit example (ml22q58) parallel interface (at 5v) parallel interface(at 3v) serial interface (at 5v) serial interface (at 3v) 150 p f aout r ese t c s wr r d d7-0 ncr1 ncr2 b usy 1 b usy 2 vbg serial optana xt xt mcu 8 4.096mhz 30pf 30pf amplifier regout dvdd avdd dgnd agnd 10 r ese t c s wr r d d7-0 ncr1 ncr2 b usy 1 b usy 2 vbg serial optana xt xt mcu 8 4.096mhz 30pf 30pf amplifier regout dvdd avdd dgnd agnd 3v nc aout r ese t c s wr r d sck di do ncr1 ncr2 b usy 1 b usy 2 vbg serial optana xt xt mcu 4.096mhz 30pf 30pf amplifier nc regout dvdd avdd dgnd agnd 3v aout r ese t c s wr r d sck di do ncr1 ncr2 b usy 1 b usy 2 vbg serial optana xt xt mcu 4.096mhz 30pf 30pf amplifier regout dvdd avdd dgnd agnd 10
fedl2250digest-11 oki semiconductor ml2250 family 33/37 package dimensions 44pin plastic qfp qfp44-p-910-0.80-2k mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5m) package weight (g) 0.41 typ. 5 rev. no./last revised 4/nov. 28, 1996 notes for mounting the su rface mount type package the surface mount type packages are ve ry susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact oki?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). (unit: mm)
fedl2250digest-11 oki semiconductor ml2250 family 34/37 33-pin w-csp p-vflga33-5.03x5.78-0.80-w package material epoxy resin ball material sn/pb package weight (g) 0.03 typ. 5 rev. no./last revised 1/nov. 30, 2004 notes for mounting the su rface mount type package the surface mount type packages are ve ry susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact oki?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
fedl2250digest-11 oki semiconductor ml2250 family 35/37 revision history page document no. date previous edition current edition description pedl2250digset-01 jun. 25, 2002 ? ? preliminary edition 1 fedl2250digset-01 oct. 15, 2002 ? ? final edition 1 fedl2250digset-02 may 12, 2003 ? ? final edition 2 ? ? added ml2251 and ml2253 fedl2250digset-03 oct. 17, 2003 ? ? eliminated mentioned items about pwm ? ? added ml2256 fedl2250digset-04 apr. 20, 2004 ? 22 added mentioned items about initial state at reset input ? ? added ml22q58 ? 10-12, 33 added ml2253/54-xxxh b(w-csp package) ? 16-18 added the pin equivalent circuits 19,20 22,23 corrected the airticle and charts about serial interface fedl2250digset-06 dec. 27, 2004 27 30,31 changed the application circuit example ? 1 modified the description of ml22q54/q58 in the ?general descri ption? section. ? 3 added ?(ML2256-XXXHB)? to the 33-pin w-csp package. ? 11 added the 33-pin w-csp package configuration of ML2256-XXXHB ? 12,13 added the ?ml2256 wcsp pin ? column? in the table. ? 12 added ml2256 to the heading above the table. ? 13 modified the description of qfp pin 24. fedl2250digset-08 jun.13, 2005 ? 17 changed the contents in the ?condition? and ?rating? columns of parameter ?power dissipation? in the t able in the ?absolute maximum ratings? section. fedl2250digset-09 sep.15, 2005 ? ? the ?digest? version is not changed.
fedl2250digest-11 oki semiconductor ml2250 family 36/37 page document no. date previous edition current edition description 15 15 partially modified the description of pin 2 (dw) in the ?pin descriptions-2? section. 25 25 - changed d3 to d0 of commands pup1, pup2, pdwn2, and ext from ?0? to ?-?. - changed d3 and d2 of commands play, start, stop, muon, sloop, cloop, and vol from ?0? to ?-?. - changed d0 of command vol from ?c2? to ?c0?. - changed d7 to d4 of command vol from ?v7?, ?v6?, and ?v5? to ?-?. - changed d7 to d0 of command fadr from ?m7 to m0? to ?f7 to f0?. 27 27 modified the description in the ?memory allocation and creating voice data? section. fedl2250full-10 dec. 1, 2006 28 28 modified the description in the ?built-in rom usage prohibited area? section. fedl2250full-11 sep.20, 2007 53 53 changed explanation of 2byte command
fedl2250digest-11 oki semiconductor ml2250 family 37/37 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. wh en planning to use the product, please ensure that the external conditions are reflected in the act ual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accide nt, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party?s industrial and intellectual prop erty right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this docu ment are intended for use in genera l electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not, unless specifi cally authorized by oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traf fic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of de termining the legality of export of these products and will take appropriate and necessary st eps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2007 oki electric industry co., ltd.

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